Integrated circuit memory devices, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs) undergo testing by the manufacturer during production and often by the end user, for example, in a memory test conducted during computer initialization. As densities of the memory device increase, so that individual IC's are capable of storing sixteen or more megabits of information, the time necessary for testing the IC's increases as well.
To reduce the testing time required, it is known in the art to place the DRAMs in a test mode. In a normal operating mode, a DRAM reads and writes one bit at a time, with exceptions for special operating modes. In the test mode, the parts are addressed in a manner which provides a series of outputs from the full array on the part in an expeditious manner, as distinguished from the memory array parts such as normal operating mode, which is intended for rapid access of data. A DRAM could be tested in the normal operating mode, but the time required to conduct exhaustive testing is excessive.
SRAMS likewise undergo testing by the manufacturer. While operating conditions of SRAM's may make performance criteria easier to define, many of the tests which must be performed on DRAMs must also be preformed on SRAMs. The testing of SRAMs must often be performed at higher speed because of the faster response expected from these parts.
In addition, there is an increased interest in providing parts which are fully characterized prior to packaging. This is desired not only because of the cost of the package, but also because there is demand for multichip modules (MCMs), in which multiple parts in die form are tested and assembled into a single unit. While there are various techniques purposed for testing, burning in and characterizing a singulated die, it would be advantageous to be able to "wafer map" the die prior to assembly with as many performance characteristics as possible. Ideally, one would want to be able to map the wafer with full device characterization.
MCMs create a particular need for testing prior to assembly, as contrasted to the economics of testing parts which are discretely packaged as singulated parts. For discretely packaged parts, if the product yield of good parts from preliminary testing to final shipment (probe-to-ship) is, for example, 95%, one would not be particularly concerned with packaging costs for the failed parts, if packaging costs are 10% of the product manufacturing costs. Even where packaging costs are considerably higher, as in ceramic encapsulated parts, testing unpackaged die is economical for discretely packaged parts when the added costs approximates that of cost of packaging divided by yield: ##EQU1## where C=cost
C.sub.DIE =manufacturing cost of functional die PA1 C.sub.ADDL.KGD =additional cost of testing unpackaged die in order to produce known good die (KGD)
Note that in the case of discretely packaged parts, the cost of the die (C.sub.DIE) is essentially not a factor. This changes in the case of MCMs: ##EQU2## Note that again C.sub.DIE is not a factor in modules having identical part types; however, the equation must be modified to account for varied costs and yields of die in modules with mixed part types. With MCMs, the cost of packaging a failed part is proportional to the number of die in the module. In the case of a .times.16 memory array module, where probe-to-ship yield of the die is 95%, the costs are: ##EQU3## so the additional costs of testing for known good die (KGD) may be 16 times the cost of testing after assembly of an unrepairable module in order to be economical. This, of course, is modified by the ability to repair failed modules.
One of the test procedures which is used to determine the viability of semiconductor integrated circuits is burnin. In the burnin procedure, the parts are exercised for a period of time with different temperature cycles, including at elevated temperatures. This procedure provides an indication of the operation of the device at the different operating temperatures, and also results in a determination of early part failures. During the burnin process, such early failures, known as "infant mortality," is predicted to occur within a particular amount of time. Therefore, if it can be determined that almost all such failures occur within the first 48 hours of burnin testing, then the burnin test can be completed within that time period. Such factors as temperature, process and device type influence when failures stop happening, so the specific burnin time period will vary with part type and other factors. In the case of testing of packaged discrete devices, each device is able to be separately monitored by external test equipment, so that the external test equipment can be used to provide an indication of the time of failure of that particular part. On the other hand, if testing is be achieved prior to the parts being singulated, it is necessary to either provide external equipment with an indication of the performance of each individual part or to record the failure of each individual part for later mapping.
In actual practice, it is common to matrix discrete parts on a DUT (device under test) board, so that each part is exercised simultaneously. It is nevertheless possible to obtain a general indication of failure by sensing the parts within the matrix.
Digital electronic circuits generally employ two-state output terminals to convey binary logic information. Such two-state output terminals produce one of two output voltages: a relatively high voltage, or a relatively low voltage. These two discernable voltages define two possible binary logic states. The low voltage defines a "0," "false," or "low" logic state. The high voltage defines a "1," "true, or "high" logic state. A voltage corresponding to a "low" is defined to be below a first threshold voltage and a voltage corresponding to a "high" is defined to be above a second, higher, threshold voltage. A voltage between the first and second thresholds is not a valid logic state, and is avoided (except during transitions between valid states) by the specific operational parameters of the electronic devices formed in the integrated circuit or other digital circuitry.
Output terminals of digital circuitry, and integrated circuits in particular, can be constructed to produce a third state. This additional or third state is not defined by a voltage level, but instead is indicated by a high impedance state at the signal terminal. Such a high impedance signal state is assumed during certain operations or under specified conditions. For example, in memory integrated circuits a high impedance state has been used on a data terminal to indicate failure during a testing mode of operation.
The high impedance state or "tri-state" does not usually correspond to a logic state. In some memory chips, such a high impedance state is useful where multiple data terminals are to be electrically connected to a common data bus. The memory of the associated computer control circuitry allows a single memory chip to operate while the data terminal of other chips are placed in a high impedance state. Thus, a single input terminal, with control circuitry selecting which of the output terminals is to be active at any given time. However, the high impedance signal state of a three-state signal terminal can also be used to convey information.
The ability to provide built-in test equipment for semiconductor integrated circuits permits testing to be accomplished in a simplified manner by means of a small number of conductors. In one configuration, testing can be accomplished by applying a supplemental conductive metal mask on the wafer and connecting the wafer to as few as two connections. A built in test circuit on each individual die can perform the test, and record the results of the test. The recorded results can then be read on the discrete die.
In one purposed system, an additional metal mask is applied to the completed wafer and connections to power and ground are made through the mask. After completion of the tests, the mask is stripped and the integrated circuit devices may be scanned for the results of the test. The results may be stored in a PROM arrangement, whereby a failure is indicated by a particular logic output of the PROM section.
The discussion of PROM storage of test information in the present invention is meant to describe the storage of information regarding the test, regardless of whether the format of the stored information conforms with standard PROM definitions and protocols. The purpose of the storage of the test information is simply to permit reading of the test results from the part subsequent to the test.